Buck Converter Circuit Design: The Core Calculations

A buck converter is usually the first switching topology a hardware engineer meets, and it is also the one most often built from a datasheet example without a full pass through the numbers. That works until the design has to hit a ripple target, survive a transient, or pass an EMC scan. This article walks through the engineering of a buck converter circuit the way it is normally taught: the operating cycle first, then duty cycle, then the three passive and stress calculations that decide whether the circuit behaves — inductor, output capacitor, and the input side plus layout. The formulas below are standard textbook relationships. The component values in any real design come from the datasheet limits, the load profile, and measured behaviour on the bench.

The buck stage and its operating cycle

A buck converter steps a higher DC input down to a lower DC output with high efficiency by switching, storing energy in a magnetic field, and then releasing it. The power stage is small: an input capacitor, a high-side switch (a MOSFET, or the internal switch of an integrated buck converter ICs), a freewheeling element (a diode in a non-synchronous design, or a low-side MOSFET in a synchronous one), an inductor, and an output capacitor. The control loop adjusts the on-time of the high-side switch to hold the output voltage against changes in input voltage and load current.

The two states of the switching cycle

In continuous conduction mode (CCM) — the normal case at medium and heavy load — the cycle has two intervals:

• On-time (switch closed, D·T_sw): the input voltage is applied across the inductor. The voltage across L is V_in − V_out, so the inductor current ramps up linearly. The inductor stores energy and the output capacitor is charged by the difference between the inductor current and the load current.
• Off-time (switch open, (1−D)·T_sw): the inductor current keeps flowing, now through the freewheeling path. The voltage across L is −V_out, so the current ramps down. Energy stored during the on-time is delivered to the output.

Steady state means the average inductor voltage over one cycle is zero — the volt-second balance. That single principle produces the duty-cycle equation in the next section, and it is worth internalising because the same reasoning extends to every other topology. The average inductor current equals the load current in CCM, and the output capacitor sees the inductor current minus the load current, which is why the output capacitor carries a triangular ripple current even though the load is steady.

CCM, DCM and the boundary

If the load current falls below half the inductor ripple current, the inductor current reaches zero during the off-time and the converter enters discontinuous conduction mode (DCM). In DCM the duty-cycle relationship changes and the small-signal behaviour differs, which matters for loop design at light load. Synchronous converters can operate in CCM down to zero load because the low-side MOSFET allows negative inductor current, at the cost of some efficiency loss at light load; non-synchronous designs simply enter DCM. The design method below assumes CCM, with the load range checked against the boundary afterwards.

Duty cycle from the voltage ratio

For an ideal buck converter, volt-second balance gives the relationship engineers use constantly:

D = V_out / V_in

If a 12 V rail must produce 5 V, the ideal duty cycle is about 0.42. Real designs include the forward drops of the switch and the freewheeling element, so the measured duty cycle is slightly higher than the ideal value; the difference is a useful sanity check when bringing up a board. Two practical consequences follow from this ratio. First, a wide input range means a wide duty-cycle range, and every parameter calculated later has to hold across that range, not just at nominal input. Second, very small duty cycles (a high input stepped far down) leave the controller little on-time resolution, and very large duty cycles approach dropout, where the converter can no longer regulate.

The switching frequency, f_sw, is chosen alongside the duty cycle. Higher frequency shrinks the inductor and capacitors but increases switching losses and layout sensitivity. Most integrated regulators specify a fixed or resistor-set frequency, and the datasheet's recommended range is the starting point rather than a free parameter.

Inductor selection: ripple current method

The inductor sets the ripple current, and the ripple current sets much of the rest of the design. The standard relationship for the on-time interval is:

ΔI_L = (V_in − V_out) × D / (L × f_sw)

In practice the method runs in reverse: choose the ripple as a fraction of the maximum load current, then solve for L. A common starting range is 20–40% of load current. Lower ripple means a larger inductor, lower core and copper losses for a given current, lower output ripple, and less stress on the output capacitor and the switches; higher ripple allows a physically smaller inductor but pushes more RMS current into the capacitors and more peak current into the switches. The choice is a trade between board area, cost, and loss, and the fraction should be stated explicitly in the design notes.

What else the inductor datasheet has to cover

• Saturation current: the peak inductor current is the load current plus half the ripple, and the saturation rating must sit comfortably above that at the maximum load and highest ambient temperature, since saturation current falls as the part heats.
• RMS and thermal current: the DC rating must cover the full load current with acceptable temperature rise in the intended copper area.
• DCR and core loss: copper loss is I_RMS² × DCR; core loss depends on the ripple amplitude and frequency. These two, plus the switch losses, dominate the efficiency budget.
• Shielding and self-resonance: unshielded parts radiate, and the self-resonant frequency must sit well above the switching frequency or the part stops behaving like an inductor.

Run the ripple calculation at both extremes of input voltage: ripple is largest at maximum V_in for a fixed output, so the peak-current check must use that case, while the thermal check uses the heaviest load.

Output capacitor and loop basics

The output capacitor has to absorb the inductor ripple current and hold the output voltage steady. The voltage ripple has two contributors: the capacitive term from charge delivered during the switching cycle, and the ESR term, which is simply the ripple current multiplied by the capacitor's equivalent series resistance. At the ripple frequencies of most designs the ESR term dominates for electrolytic parts, which is why low-ESR capacitors or ceramics are used at the output and why the ESR specification is read as carefully as the capacitance. The capacitor also carries an RMS ripple current, and its ripple-current rating must be respected or the part will run hot and age quickly.

Beyond ripple, the output capacitor is one half of the control loop's behaviour. The power stage contributes a double pole (from L and C) and the capacitor's ESR adds a zero; the controller's compensation network has to place its poles and zeros so the loop crosses over at a sensible fraction of the switching frequency with adequate phase margin. That is a subject for its own article, but two practical points belong here: the capacitor's ESR and capacitance tolerance affect loop stability, so a capacitor substitution is a design change and not a purchasing decision; and a transient load step is limited by the same capacitance and ESR, so the ripple calculation and the transient requirement should be checked together.

Input capacitor, diode/MOSFET stresses and layout rules

The input capacitor is the most under-specified part in many first designs. During the on-time the input capacitor supplies the pulsed current drawn by the high-side switch; the resulting RMS current in the input capacitor is approximately I_out × √(D(1−D)), which peaks at D = 0.5 and is far larger than most engineers expect. The capacitor must be rated for that ripple current, placed close to the switch pair, and combined with a small ceramic for high-frequency decoupling. A poor input capacitor shows up as input voltage sag, jitter, and radiated emissions.

Device stresses

• High-side switch: blocks V_in plus switching-node ringing, conducts the full load current plus half the ripple, and carries the switching loss. The voltage rating needs margin over the maximum input, including transients.
• Freewheeling diode or low-side MOSFET: blocks V_in during the on-time and conducts during the off-time. In a synchronous design the low-side MOSFET's body diode conducts briefly at each commutation, so its reverse recovery and the dead time matter.
• Gate drive: the gate charge has to be supplied at f_sw, and that loss belongs in the efficiency budget along with the switching and conduction losses.

Layout rules

The high-current loop — input capacitor, high-side switch, low-side switch or diode, and back to the input capacitor — must be as small as possible, because its area sets the radiated field and its stray inductance sets the switching-node ringing. The inductor follows immediately, the output capacitor sits at the load, and the feedback divider is taken from the output capacitor terminals with a short, quiet trace kept away from the switch node. The switch node copper should be small: it is the loudest net on the board. A ground plane under the power stage and a single-point connection between power and signal ground finish the standard set of rules. These layout habits carry over directly to other topologies; if the next design steps up instead of down, the same loop-area discipline applies, as covered in our article on boost converter circuit design.

Worked in this order — operating cycle, duty cycle, inductor ripple, output capacitor and loop, then input side, stresses, and layout — a buck converter circuit becomes a set of defensible numbers rather than a copied schematic. The remaining step is measurement: ripple, efficiency, and transient response on the bench, at both input extremes and over the load range. The DC-DC converters category lists the regulator families and evaluation hardware that support this workflow.